Intelligent Chip Layout Synthesis and Analysis

Layout synthesis is a process that converts the logic description of a chip into a physical layout for manufacturing. In layout synthesis of very large scale integration (VLSI), there are two major steps: placement in which all the electronic components are properly located in the design area and routing in which the layout of wires is generated to realize the interconnection between the connected electronic components. Due to the high complexity of layout synthesis for modern integrated circuits (ICs), electronic design automation (EDA) algorithms are widely used to automatically generate physical chip layout while simultaneously optimizing multiple objectives, including but not limited to area, timing, power, and manufacturability. In this artificial intelligence (AI) era, with advanced technology node of ICs, novel EDA algorithms are needed to satisfy newly emerging demands on layout synthesis. Besides, layout analysis which extracts useful information from a chip layout to facilitate the improvement of the original design flow is attracting more and more attention from both academia and industry.New demands on layout synthesis incur special placement and routing problems beyond classical ones. In this thesis, we study a deep neural network (DNN) placement problem brought by the rising AI chips and a bus routing problem with the constraint of routing topology consistency for the ease of signal synchronization. To solve the former one, we propose an effective placement engine named CU.POKer to place DNN workloads onto the execution cores of an AI chip. In CU.POKer, a two-step search scheme and a data-path-aware placement algorithm are developed accordingly to bring high quality. For bus routing, we propose a maze routing-based algorithm named MARCH that maintains the topology consistency by routing the bits in a bus concurrently and achieves efficiency by applying a hierarchical routing scheme.Regarding layout analysis, we explore both machine learning (ML)-based analysis and geometry-based analysis. For ML-based analysis, we propose PROS that can accurately forecast routing congestion at the placement stage which can then be utilized to perform routability optimization and routed wirelength estimation. For geometry-based analysis, we propose a method to detect the largest repeating (LR) patterns in a flat chip layout after routing. This method is carefully designed to construct LR patterns in a recursive manner. The detected LR patterns can be used to effectively reduce repetitive and redundant data process and data storage in the mask data preparation flow.版圖合成是一個將芯片的邏輯描述轉換成一個用於製造的物理布局的過程。在超大規模集成電路（Very Large Scale Integration，VLSI）的版圖合成過程中，有兩個主要步驟：布局，即把所有的電子元件合理地擺放在設計區域內；布線，即生成電路框架以實現電子元件之間的相互連接。由於現代集成電路（Integrated Circuit，IC）版圖合成的高度復雜性，電子設計自動化（Electronic Design Automation，EDA）算法被廣泛應用於自動化生成物理芯片版圖，同時優化多個目標，這些目標包括但不限於芯片面積、時序、功耗和可製造性。在當今人工智能（Artificial Intelligence，AI）時代，伴隨著集成電路的先進技術節點，需要新的EDA 算法來滿足新出現的版圖合成需求。此外，從芯片版圖中提取有用信息以優化原設計流程的"版圖分析"也正吸引著學術界和工業界越來越多的關註。版圖合成的新需求引出了不同於傳統問題的特殊布局布線問題。在本文中，我們研究了一個由興起的AI 芯片帶來的深度神經網絡（Deep Neural Network，DNN）布局問題，以及一個為便於信號同步而具有電路拓撲一致性約束的總線布線問題。為了解決前一個問題，我們提出了一個名為CU.POKer 的布局工具來有效地將DNN 的計算任務部署到AI 芯片的處理核心上。在CU.POKer 中，我們相應地開發了一個兩階段搜索方案和一個數據流導向的布局算法，以帶來高質量的布局結果。對於總線布線，我們提出了一種名為MARCH 的基於迷宮演算法的布線算法，該算法通過對總線中所有位進行並發布線來保持拓撲結構的一致性，並通過使用多級布線方案來實現高效。關於版圖分析，我們探討了基於機器學習（Machine Learning，ML）的分析和基於幾何的分析。對於基於ML 的分析，我們提出了PROS，它可以在布局階段準確地預測布線時的線路擁塞情況，然後利用預測的結果來優化可布線性以及估計布線後的線長。對於基於幾何的分析，我們提出了一種方法來檢測布線後平面芯片版圖中的最大重復（largest repeating，LR）版圖樣式。這個方法被精心得設計以遞歸的形式來構建出LR 版圖樣式。檢測到的LR 版圖樣式可以用來有效地減少掩膜數據準備流程中的重復和冗余的數據處理和數據存儲。CHEN, Jingsong.Ph.D. Chinese University of Hong Kong 2021.Includes bibliographical references (leaves )Abstracts in English and Chinese.Title from PDF title page (viewed on ...