Plug-and-Play Tunable and High-Performance Time-to-Digital Converter as IP-Core for Xilinx FPGAs

In this contribution, we present the implementation of a tunable, high-performance, multi-channel, Tapped Delay- Line (TDL) based, plug-and-play, Time-to-Digital Converter (TDC) IP-Core for Xilinx Field Programmable Gate Arrays (FPGAs) and System-on-Chips (SoCs). The term tunable refers to the easy set of Full-Scale Range (FSR), resolution (LSB), and the number of channels. In particular, we can tune the LSB up to hundreds of femtoseconds, the FSR up to unit of seconds, and the number of channels up to 16. In addition, the TDC presents a dead-time between two consecutive measures lower than 5 ps, which means maximum measurement rate up to 200 Msps per channel. To obtain such high-resolution over a wide dynamic-range the measurement is performed according to the Nutt-Interpolation technique. The timestamp of each channel is composed of a coarse part, that defines the FSR obtained from sampling a counter with tunable bit-dimension, and of a fine part, obtained from the Super Wave Union (SuperWU) subinterpolation algorithm over the TDLs. The number of taps of the TDLs and the number of TDLs in parallel in each channel are tunable, making the SuperWU algorithm generate a Virtual-TDL (V-TDL) composed by “so called” virtual-taps, whose virtual propagation delays define the LSB. From the design point of view, the TDLs are implemented with the carry-chains, available into the fabric of the Xilinx device. A decoder used to perform the thermometric-to-binary conversion and a “bin-by-bin” dynamic calibrator per channel are used to correct the bubble-errors and to compensate at best the non-linearity, and the temperature drift introduced by the different propagation delays of the carrychains blocks. The IP-Core is fully tested on different families of Xilinx 7-Series, UltraScale and UltraScale+ FPGAs and SoCs