In nuclear physics time-resolved experiments, the improvement in temporal resolution of detectors from nanoseconds to hundreds of picoseconds, and the increasing of the number of channels required in the applications move the research through the design of Time-to-Digital Converter addressable to programmable logic device, i.e. Field-Programmable Gate Array(FPGA) and System-on-Chip (SoC). In this contribution, we present the implementation strategy of a resource-saving, multi-phase Shift-Clock Fast-Counter (SCFC) Time-to-Digital Converter (TDC) designed to be implemented on FPGA. The SCFC-TDC has been designed to guarantee hundreds of picoseconds resolution over a microseconds full-scalerange (FSR) with hundreds of channels. In order to rea...