A new recursive multibit recoding algorithm for high-speed an low-power multiplier.

International audienceIn this paper, a new recursive multibit recoding multiplication algorithm is introduced. It provides a general space-time partitioning of the multiplication problem that not only enables a drastic reduction of the number of partial products (n/r), but also eliminates the need of pre-computing odd multiples of the multiplicand in higher radix (ß≥8) multiplication. Based on a mathematical proof that any higher radix ß=2r can be recursively derived from a combination of two or a number of lower radices, a series of generalized radix ß=2r multipliers are generated by means of primary radices : 21 , 22, 25, and 28. A variety of higher-radix (23 - 232) two's complement 64x64 bit serial/parallel multipliers are implemented on Virtex-6 FPGA and characterized in terms of multiply-time, energy consumption per multiply-operation, and area occupation for r value varying from 2 to 64. Compared to reference algorithm, savings of 8%, 52%, 63% are respectively obtained in terms of speed, power, and area. In addition, a new low-power and highly-flexible radix 2r adapted technique for a multi-precision multiplication is presented