Probing defects generation during stress in high-\u3ba/metal gate FinFETs by random telegraph noise characterization

In this work, we report about defects generation in the oxide layer of n-FinFETs during stress. Defects generation is probed using RTN traces collected at both the drain and the gate. A stress/measure approach is used to monitor the characteristics of the device, including RTN, at different levels of cumulative stress. Indicators derived from IG-VG and ID-VG measurements suggest defects generation to occur away from the channel. This is confirmed by the RTN analysis, which shows that drain and gate RTN events are completely uncorrelated. The detailed analysis of the RTN properties at different stress levels shows that an increase of the gate leakage is accompanied by changes in the gate RTN properties, while the drain RTN properties are rarely affected by the stress. This further proves that stress is associated with defects generation deep in the oxide layer, far away from the channel. This result is in contrast to what reported for planar FETs and suggests that, in n-FinFETs, the root cause of ID RTN might differ from the one causing SILC and IG RTN