A Charge-Trapping Model for the Fast Component of Positive Bias Temperature Instability (PBTI) in High-k Gate-Stacks
- VANDELLI, LUCA
- LARCHER, Luca
- PADOVANI, ANDREA
- Veksler, Dmitry
- Bersuker, Gennadi
- Matthews, Kenneth
Publication date
January 2014
DOI Publisher
Institute of Electrical and Electronics Engineers (IEEE)Abstract
We propose a physical model for the fast component (<1 s) of the positive bias temperature instability (PBTI) process in SiOx/HfO2 gate-stacks. The model is based on the electron–phonon interaction governing the trapping/emission of injected electrons at the preexisting defects in the dielectric stack. The model successfully reproduces the experimental time dependences of the VTH shift on both stress voltage and temperature. Simulations allow the extraction of the physical characteristics of the defects contributing to PBTI, which are found to match those assisting the leakage current in these stacks (i.e., oxygen vacancies)
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