Modified Gating Techniques for Power and Speed Optimization in Arithmetic Circuits

As the threshold voltage is reduced due to voltage scaling in CMOS technology, it leads to increase in sub-threshold leakage current and hence static power dissipation. In this paper a power reduction technique named high speed drain gating is proposed to yield high speed, low power consumption and fast discharge. In these techniques two sleep transistors are employed, one to conserve leakage power and the other to reduce propagation delay. Simulations are performed using Tanner EDA tool in 90nm process technology. Comparative analysis of the present techniques is tabulated using 4x2 encoder and NAND gate