Design and Implementation of Parallel FIR Filter Using High Speed Vedic Multiplier

The demand for high speed processing has been increasing as a result of expanding computer and signal processing applications. Higher throughput arithmetic operations are important to achieve the desired performance in many signal processing and image processing applications. One of the key arithmetic operations in such applications is multiplication which determines the performance of the entire system. Thus the optimization of the multiplier speed and area is a challenge for many processors. This challenge has been successfully overcome by the use of ancient Vedic multiplier. This paper illustrates design and implementation of parallel Finite Impulse Response (FIR) filters using Vedic mathematics based Urdhva Tiryabhyam algorithm. The system is aiming to reduced propagation delay and area of the filter. The proposed system based on Vedic multiplier is compared with that on conventional multiplier on the basis of resources and time required for processing given data. The comparison shows the 36.29% and 15.70% reduction in propagation delay for two-parallel and three-parallel FIR filter using Vedic multiplier as compared to that of conventional multiplier. The architecture is coded in VHDL and synthesized and simulated by using Xilinx Design Suite 13.1 ISE