Hardware Synthesis of Chip Enhancement Trasformations in Hardware Description Language Environment

Human analyze different sight in daily life images to perceive their environment. More than 99% of the activity of human brain is involved in processing images from the visual cortex. A visual image is rich in information and can save thousand words. Many real world images are acquired with low contrast and unsuitable for human eyes to read, such as industrial and medical X-ray images. Image enhancement is a classical problem in image processing and computer vision. The image enhancement is widely used for image processing and as a preprocessing step in texture synthesis, speech recognition, and many other image/video processing applications. The main challenge is to transpose the validated algorithms into a language as hardware description languages. It is also the need that the input and output data files should be reshaped to match the binary content permitted into the hardware simulators. Research focuses on Simulation, Design and Synthesis of 2D and 3D Image enhancement chip in Hardware description language (HDL) Environment. The chip implementation of image enhancement algorithm is done using Discrete Wavelet Transformation (DWT) and Inverse Modified Discrete Cosine Transformation (IMDCT). Hardware chip modeling and simulation is done in Xilinx 14.2 ISE Simulator. Synthesis environment is carried out on Diligent Sparten-3E FPGA. . Image enhanced values are seen in the waveform editor of Modelsim software