Novel Voltage Triggered Electrostatic Discharge (Esd) Detection Circuit

A novel 2×VDD-tolerant electrostatic discharge (ESD) detection circuit which uses only low-voltage devices is proposed in a 0.18 um CMOS process. Under normal operating conditions, all the devices are free from over-stress voltage threat. Our proposed detection circuit achieves a high triggering efficiency with a much smaller footprint. Comparing with the RC based detection circuit, our proposed circuit is a voltage triggered detection circuit which is immune to false triggering under the fast power-up events. SPICE simulation is carried out to evaluate the detection circuit, and the simulation results suggest that the proposed circuit could be used as a reliable 2×VDD-tolerant I/O buffer