Correlation factors between different ESD pulse types for different back-end-of-line (BEOL) metal-line topologies have been studied to support system-level on-chip ESD design. The component level (HMM, HBM, and TLP on a wafer) and system-level (IEC gun contact on package) ESD stresses were correlated followed by extraction of correlation factors between the IEC/HMM and TLP, as well as the HBM and TLP supported by analytical approximation. The major conclusions were verified using the thermal coupled mixed-mode simulation analysis. © 2013 IEEE
International audienceIn order to ensure reliability of systems early in the design phase, it is bec...
Correlation between near-field EMI scan and ESD susceptibility scan of a cellphone CPU IC is investi...
Goal: Evaluate component level design constraints to assist in system level electrostatic discharge ...
Correlation factors between different ESD pulse types for different back-end-of-line (BEOL) metal-li...
Correlation factors between different ESD pulse types for different back-end-of-line (BEOL) metal-li...
Passing voltage levels measured from the human metal model tester are correlated with the failure cu...
Electrostatic Discharges (ESD) are one of the main reliability threats in modern electronics. Design...
Passing voltage levels measured from the human metalmodel tester are correlated with the failure cur...
Abstract — There are several models which try to describe the waveforms and damage produced by an el...
International audienceA new setup for generating a Human Metal Model compliant waveform with a TLP i...
The electrical characterization of devices and circuits regarding their electrostatic discharge (ESD...
An on-wafer human metal model ESD measurement setup with voltage and current waveform measurement ca...
This paper shows that device robustness for system level ESD scales linearly with device width. Rela...
Correlation problems for HBM-ESD testing result from the complex interaction between device and test...
A custom test board facilitates transmission line pulse (TLP) characterization of the external pins ...
International audienceIn order to ensure reliability of systems early in the design phase, it is bec...
Correlation between near-field EMI scan and ESD susceptibility scan of a cellphone CPU IC is investi...
Goal: Evaluate component level design constraints to assist in system level electrostatic discharge ...
Correlation factors between different ESD pulse types for different back-end-of-line (BEOL) metal-li...
Correlation factors between different ESD pulse types for different back-end-of-line (BEOL) metal-li...
Passing voltage levels measured from the human metal model tester are correlated with the failure cu...
Electrostatic Discharges (ESD) are one of the main reliability threats in modern electronics. Design...
Passing voltage levels measured from the human metalmodel tester are correlated with the failure cur...
Abstract — There are several models which try to describe the waveforms and damage produced by an el...
International audienceA new setup for generating a Human Metal Model compliant waveform with a TLP i...
The electrical characterization of devices and circuits regarding their electrostatic discharge (ESD...
An on-wafer human metal model ESD measurement setup with voltage and current waveform measurement ca...
This paper shows that device robustness for system level ESD scales linearly with device width. Rela...
Correlation problems for HBM-ESD testing result from the complex interaction between device and test...
A custom test board facilitates transmission line pulse (TLP) characterization of the external pins ...
International audienceIn order to ensure reliability of systems early in the design phase, it is bec...
Correlation between near-field EMI scan and ESD susceptibility scan of a cellphone CPU IC is investi...
Goal: Evaluate component level design constraints to assist in system level electrostatic discharge ...