The impact of strain-induced oxide trap charge on the performance and reliability of fully silicided (FUSI)-metal-gate silicon-on-insulator (SOI) MOSFETs is investigated. High strain from a contact etch stop layer (CESL) in FUSI-gate transistors increases channel mobility and drain current driving. A CESL nMOSFET with a thick SOI demonstrates increased hot-electron degradation than its thin SOI counterpart. However, a ring oscillator using thick SOI transistors shows less gate delay due to enhanced drain current. Strained p-channel transistors with a large SOI thickness are more vulnerable to negative bias temperature instability. The oxide trap charge also plays an important role in the circuit performance degradation of RF low-noise and p...
International audienceWe study the effects of a strained contact etch stop layer (CESL) on fully dep...
DoctorAs the gate dimensions of MOSFET are continuously scaled down, the conventional SiO2-based tra...
As device scaling becomes more and more difficult, semiconductor industry seeks alternative ways to ...
The impact of strain-induced oxide trap charge on the performance and reliability of fully silicided...
The impact of strain-induced oxide trap charge on the performance and reliability of fully silicided...
[[abstract]]In this letter, we investigate the effects of oxide traps induced by various silicon-on-...
[[abstract]]In this letter, we investigate the effects of oxide traps induced by various silicon-on-...
The impact of strain induced oxide trap charge on the performance and reliability of contact etch st...
[[abstract]]This study investigates the effects of oxide traps induced by SOI of various thicknesses...
[[abstract]]The impact of strain induced oxide trap charge on the performance and reliability of con...
[[abstract]]In this paper, the impact of strain engineering on device performance and reliability fo...
[[abstract]]In this work, the impact of strain engineering on device performance and reliability for...
[[abstract]]For SOI nMOSFET, the impact of high tensile stress contact etch stop layer (CESL) on dev...
The conventional planar bulk MOSFET is difficult to scale down to sub-20nm gate length, due to the w...
International audienceWe study the effects of a strained contact etch stop layer (CESL) on fully dep...
International audienceWe study the effects of a strained contact etch stop layer (CESL) on fully dep...
DoctorAs the gate dimensions of MOSFET are continuously scaled down, the conventional SiO2-based tra...
As device scaling becomes more and more difficult, semiconductor industry seeks alternative ways to ...
The impact of strain-induced oxide trap charge on the performance and reliability of fully silicided...
The impact of strain-induced oxide trap charge on the performance and reliability of fully silicided...
[[abstract]]In this letter, we investigate the effects of oxide traps induced by various silicon-on-...
[[abstract]]In this letter, we investigate the effects of oxide traps induced by various silicon-on-...
The impact of strain induced oxide trap charge on the performance and reliability of contact etch st...
[[abstract]]This study investigates the effects of oxide traps induced by SOI of various thicknesses...
[[abstract]]The impact of strain induced oxide trap charge on the performance and reliability of con...
[[abstract]]In this paper, the impact of strain engineering on device performance and reliability fo...
[[abstract]]In this work, the impact of strain engineering on device performance and reliability for...
[[abstract]]For SOI nMOSFET, the impact of high tensile stress contact etch stop layer (CESL) on dev...
The conventional planar bulk MOSFET is difficult to scale down to sub-20nm gate length, due to the w...
International audienceWe study the effects of a strained contact etch stop layer (CESL) on fully dep...
International audienceWe study the effects of a strained contact etch stop layer (CESL) on fully dep...
DoctorAs the gate dimensions of MOSFET are continuously scaled down, the conventional SiO2-based tra...
As device scaling becomes more and more difficult, semiconductor industry seeks alternative ways to ...