In this paper, we propose an array-based architecture for DCT computation with high scalability. The scalable architecture can perform DCT computations for 15 different zones and 8 different precisions to achieve quality scalability for DCT coefficients. Due to the quantization process in video coding, the quality can still be retained for larger quantization parameter. We show the detailed comparisons between the quality scalability and the tradeoff factors, i.e., throughput, hardware resources, clock frequencies, and power consumptions. © 2008 IEEE
A novel technique is proposed to reduce the computational complexity of discrete cosine transform (D...
In this paper, we propose FPGA-based scalable architecture for DCT computation using dynamic partial...
Currently different types of transform techniques are used by different video codecs to achieve data...
In this paper, we propose an array-based architecture for DCT computation with high scalability. The...
In this paper, we present a unified architecture that can perform Discrete Cosine Transform (DCT), I...
The applicability of MPEG video coding can be improved by scaling both the algorithmic complexity an...
In this paper, we present a unified architecture that can perform Discrete Cosine Tran form (DCT), I...
This paper proposes an area-efficient fixed-point architecture for the computation of the discrete c...
This paper discusses a novel algorithm that combines the DCT with the quantizer to achieve energy sc...
This work presents a flexible VLSI architecture to compute the N-point DCT. Since HEVC supports diff...
Abstract—In this paper, we present area- and power-efficient architectures for the implementation of...
Video coding is widely used in our daily life. Due to its high computational complexity, hardware im...
Discrete Cosine Transform ( DCT), which is an important component of image and video compression, is...
In this article, we propose field programmable gate array-based scalable architecture for discrete c...
In this article, we propose field programmable gate array-based scalable architecture for discrete c...
A novel technique is proposed to reduce the computational complexity of discrete cosine transform (D...
In this paper, we propose FPGA-based scalable architecture for DCT computation using dynamic partial...
Currently different types of transform techniques are used by different video codecs to achieve data...
In this paper, we propose an array-based architecture for DCT computation with high scalability. The...
In this paper, we present a unified architecture that can perform Discrete Cosine Transform (DCT), I...
The applicability of MPEG video coding can be improved by scaling both the algorithmic complexity an...
In this paper, we present a unified architecture that can perform Discrete Cosine Tran form (DCT), I...
This paper proposes an area-efficient fixed-point architecture for the computation of the discrete c...
This paper discusses a novel algorithm that combines the DCT with the quantizer to achieve energy sc...
This work presents a flexible VLSI architecture to compute the N-point DCT. Since HEVC supports diff...
Abstract—In this paper, we present area- and power-efficient architectures for the implementation of...
Video coding is widely used in our daily life. Due to its high computational complexity, hardware im...
Discrete Cosine Transform ( DCT), which is an important component of image and video compression, is...
In this article, we propose field programmable gate array-based scalable architecture for discrete c...
In this article, we propose field programmable gate array-based scalable architecture for discrete c...
A novel technique is proposed to reduce the computational complexity of discrete cosine transform (D...
In this paper, we propose FPGA-based scalable architecture for DCT computation using dynamic partial...
Currently different types of transform techniques are used by different video codecs to achieve data...