Performance Evaluation Of Fpga-Based Hardware Accelerator: A Case Study

FPGA has been used as hardware accelerators for many scientific applications in recent years. This paper investigates performance of FPGA hardware accelerator with cell unit capable of floating point operation through a case study of Dirichlet Boundary Problem (DBP). In this paper, we concentrate on the accelerator performance with real-time results updated in PC memory. FPGA architecture for the DBP application is designed and implemented on FPGA computing card with a Xilinx XC4VLX100 chip. A performance model is established for the FPGA implementation based on communication time for data sharing between host PC and FPGA and execution time within FPGA accelerator. Experiment environments and hardware resource utilization are discussed. Finally, the model is analyzed and verified to find the optimum performance