In this paper, we propose a packet-based, off-chip, multi-processor/memory simulation framework to measure the performance of interconnect architectures linking network processors and memories on line cards. The simulator architecture utilizes software methodologies, such as STL, pure virtual functions, and singleton classes, which provide a great deal of modularity in constructing the physical and functional system modules and allow future scalability. The simulator includes performance enhancing features to route, switch, and control packet flows in order to minimize congestion spots within the interconnects and packet loss. Packets are routed adaptively among processors and memories following a non-uniform traffic patterns. The simulator...
Networks of workstations (NOWs) are becoming increas-ingly popular as a cost-effective alternative t...
This paper describes a discrete-event simulator designed for the analysis of communication switching...
Communication is an important component in determining the overall performance of a distributed memo...
In this work, we propose a visual, custom-designed, event-driven interconnect simulation framework t...
In this work, we propose a visual, custom-designed, event-driven interconnect simulation framework t...
Network line, cards are experiencing ever increasing line rates, random data bursts, and limited spa...
Network line cards are experiencing ever increas-ing line rates, random data bursts, and limited spa...
In this paper, we propose two off-chip interconnect architectures, called 3D-interconnects, to commu...
In this work, we present off-chip communications architectures for line cards to increase the throug...
Deep layer processing and increasing line rates present a memory challenge to processor-memory commu...
Deep layer processing and increasing line rates present a memory challenge to processor-memory commu...
In this paper, we propose two hypercube-based, off-chip interconnect architectures, called 3D-interc...
In this paper, we propose two hypercube-based, off-chip interconnect architectures, called 3D-interc...
Simulation is a tool that can be used to assess functionality and performance of communication netwo...
The principal modelling and simulation features of multistage interconnection networks operating in ...
Networks of workstations (NOWs) are becoming increas-ingly popular as a cost-effective alternative t...
This paper describes a discrete-event simulator designed for the analysis of communication switching...
Communication is an important component in determining the overall performance of a distributed memo...
In this work, we propose a visual, custom-designed, event-driven interconnect simulation framework t...
In this work, we propose a visual, custom-designed, event-driven interconnect simulation framework t...
Network line, cards are experiencing ever increasing line rates, random data bursts, and limited spa...
Network line cards are experiencing ever increas-ing line rates, random data bursts, and limited spa...
In this paper, we propose two off-chip interconnect architectures, called 3D-interconnects, to commu...
In this work, we present off-chip communications architectures for line cards to increase the throug...
Deep layer processing and increasing line rates present a memory challenge to processor-memory commu...
Deep layer processing and increasing line rates present a memory challenge to processor-memory commu...
In this paper, we propose two hypercube-based, off-chip interconnect architectures, called 3D-interc...
In this paper, we propose two hypercube-based, off-chip interconnect architectures, called 3D-interc...
Simulation is a tool that can be used to assess functionality and performance of communication netwo...
The principal modelling and simulation features of multistage interconnection networks operating in ...
Networks of workstations (NOWs) are becoming increas-ingly popular as a cost-effective alternative t...
This paper describes a discrete-event simulator designed for the analysis of communication switching...
Communication is an important component in determining the overall performance of a distributed memo...