The design of a data compression system

The design is given for a Data Compression System which utilizes the latest Large Scale Integrated circuitry. A maximum of 64 analog channels can be digitized by a Time Multiplexed PCM System. The digital output of the PCM system is then checked for redundancy by the Central Processor Unit. Redundancy is determined by either the Zero Order Predictor or First Order Interpolator data compression algorithm, Non-redundant outputs of the Central Processor Unit are stored by the Output Buffer Memory to enable continuous synchronous transmission. Once received, the compressed data is reconstructed by a general purpose digital computer. The reconstruction program inserts the redundant data removed by the compressor and routes each channel to its final destination.Electrical and Computer Engineering, Department o