A very simple linear folding architecture for subranging ADC is presented. The preprocessing analog structure is constituted with 2n (with n number of bits) parallel circuits made with a simple subtracting node and with a series of two MOS switches able to join the functionalities of DAC, summing node and amplifier typical of classical subranging ADC. To validate the idea an accurate simulation of the single channels and of the whole structure has been realized
A 8-bit 150MHz low-power CMOS folding and interpolating analog-to-digital converter with a fully-fol...
Abstract—An analog-to-digital converter (ADC) architecture is described which utilizes mixing instea...
206 p.This dissertation presents a new 10-bit subranging analog-to-digital converter (ADC) dedicated...
A very simple linear folding architecture for subranging ADC is presented. The preprocessing analog...
A simplified architecture of subranging pure linear folding ADC is proposed. The device is based on...
A very simple circuit for a 3-bits discrete pure linear analog preprocessing folding ADC is present...
This paper presents a novel encoding scheme based on the residue number systems for folding ADC to e...
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
A 10-bit two-step subranging folding analog-to-digital converter (ADC) that converts signal at 500 M...
A simplified 3 –bits discrete pure linear analog preprocessing folding ADC architectur
This paper proposes a new structure of a high speed analog-to-digital converter (ADC) with high reso...
This paper presents an 8-bit low power cascaded folding and interpolating analog-to-digital converte...
A 6-bit 250MHz low-power CMOS fully-folding analog-to-digital converter is designed in a 0.5??m stan...
The dynamical characteristics simulation results of the analog signal folding circuit for comparator...
A new architecture of subranging ADC is proposed. Against a little increase of the number of compar...
A 8-bit 150MHz low-power CMOS folding and interpolating analog-to-digital converter with a fully-fol...
Abstract—An analog-to-digital converter (ADC) architecture is described which utilizes mixing instea...
206 p.This dissertation presents a new 10-bit subranging analog-to-digital converter (ADC) dedicated...
A very simple linear folding architecture for subranging ADC is presented. The preprocessing analog...
A simplified architecture of subranging pure linear folding ADC is proposed. The device is based on...
A very simple circuit for a 3-bits discrete pure linear analog preprocessing folding ADC is present...
This paper presents a novel encoding scheme based on the residue number systems for folding ADC to e...
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
A 10-bit two-step subranging folding analog-to-digital converter (ADC) that converts signal at 500 M...
A simplified 3 –bits discrete pure linear analog preprocessing folding ADC architectur
This paper proposes a new structure of a high speed analog-to-digital converter (ADC) with high reso...
This paper presents an 8-bit low power cascaded folding and interpolating analog-to-digital converte...
A 6-bit 250MHz low-power CMOS fully-folding analog-to-digital converter is designed in a 0.5??m stan...
The dynamical characteristics simulation results of the analog signal folding circuit for comparator...
A new architecture of subranging ADC is proposed. Against a little increase of the number of compar...
A 8-bit 150MHz low-power CMOS folding and interpolating analog-to-digital converter with a fully-fol...
Abstract—An analog-to-digital converter (ADC) architecture is described which utilizes mixing instea...
206 p.This dissertation presents a new 10-bit subranging analog-to-digital converter (ADC) dedicated...