Doctor of Philosophy

dissertationThe relative timed methodology produces up to 1/2 to 1/20th power at the same performance in asynchronous modules compared to industry best practice. Commercial EDA tools are developed under the assumption that users apply a traditional clocked design methodology. They are highly optimized to support this approach. However, this leaves substantial room for improvement when applying alternative design approaches, such as asynchronous design. One approach would be to build completely custom tool suites for each alternative design methodology. Another is to provide external algorithms or directives to enable improved design quality using the commercial EDA tools that directly support clocked design methodology. We adopt the latter philosophy. We were able to achieve an average of 1/3rd the power with timed asynchronous circuits than the clocked design using commercial EDA. This research enhances current RT flows using commercial EDA tools to achieve a 20-25% et2 improvement with benefits in power and performance both by applying timing and placement optimization techniques. The commercial EDA tools have been enhanced to utilize the full potential of timed asynchronous circuits by : (a) Fixing, variation due to electronic design automation (EDA) tools and custom flows that are caused by specific optimization for clocked design or lack of necessary data for an alternative design methodology. We add information through relative placement (RP) to make physical design work better. (b) Implementing, that the timing closure engine ensures no negative slack on each timing path by optimizing values for each constraint, since relative timed design can have millions of timing constraints. (c) Incorporating, a machine learning based solution, which is provided to time relative timed circuits. It allows us to utilize the design architecture data and performance path along with the path type information to sign off timing on a design