A model of the off-behaviour of 4H–SiC power JFETs

A physical model of the off-behaviour of Vertical Junction Field Effect Transistors (VJFETs) up to their blocking voltage limit is presented. Since the drain current, ID, of these devices strongly depends on the amount of the voltage barrier occurring in the channel, the model is capable to describe the drain voltage dependence of the voltage barrier and of ID from VDS = 0 V up to maximum VDS value (kV) sustained from device and to describe the effects of geometry and doping of channel. The accuracy of the model is proven by comparing the ID–VDS curves with numerical simulations of devices designed with different gate depth, channel width, and epilayer thickness. The agreement between model, numerical simulations and literature data confirms the capability of model to describe the ID–VDS curves of devices having a pentode or triode like behaviour