A novel design method to prevent SEPIC’s instability

This paper presents a novel method for optimal selection of passive components of current controlled SEPIC dc-dc switching regulators, aimed at preventing converterpsilas current loop instability. The source of current loop instability is a couple of complex right half plane zeros of open loop duty-to-output transfer function. The stability is achieved by identifying real inductors and capacitors whose parameters ensure the presence of one right half plane zero only in the duty-to-output transfer function. A design example is discussed, which illustrates how to ensure stable SEPIC operation by means of the proposed design method