Optimized tolerance design of feedback compensation networks for voltage regulators

A reliable yield evaluation tool, useful for circuit tolerance design, is presented in this paper. It is based on a recursive divide-and-conquer algorithm that verifies the feasibility of each subset of the tolerance region (TR) under test. Such a check is performed by means of interval arithmetic (IA), thus giving a high robustness and reliability to the method and supplying a lower bound and all upper bound for the yield value pertinent to the tolerance region under test. Thanks to the use of IA, the method allows detecting possible unfeasibility pockets included in the designed TR. Such a circumstance occurs if the design problem shows a nonconvex and not simply connected region of acceptability and this fact has not been accounted for during the TR optimization design stage. Any portion of the boundaries of the region of acceptability that is included in the tolerance region is identified and the analysis is refined across it. The technique proposed in the paper has been applied to the tolerance design of two different possible realizations of the feedback control network of a voltage-mode regulated DC-DC converter