A Novel Architecture and Simulation for Executing Decoupled Threads in Future 1-Kilo-Core Chip

T-Star (T*) is an ISA-extension that supports a promising execution model to exploit Thread Level Parallelism (TLP) in designing for the next generation chip. This model relies on DataFlow principles. A compiler partitions the program into non-blocking threads which start consuming their own data frames when all their inputs become ready. Especially for future systems composed of thousands of cores on a single chip, we believe that this model is very efficient because it allows less synchronization delays among parallel threads. In this paper we describe some initial works towards simulating 1 kilo-core DataFlow enable chips