Scheduling and NoC Traffic Reduction in T-SDF Architecture

As transistor size shrinks and chip complexity increases it is possible to place more transistor onto a singe chip, and thus it is possible to integrate more then one processor on a single chip. Clock frequency is also increased, and because of wire delay it is not possible to reach all parts of a chip in a single clock cycle, and interconnection network is becoming a bottleneck in such systems. Our research is focused on creating a multiprocessor on chip architecture based on SDF architecture, by placing multiple processing cores on a single chip, and by interconnecting them to work together. We are investigating possible ways to connect cores, ways in which threads are scheduled on individual cores and ways to reduce network traffic, specially the coherence traffic by using PSCR protocol