Real Time Simulation and Hardware in the Loop Methods for Power Electronics Power Distribution Systems

System level testing of Power Electronics Power Distribution Systems (PEPDS) can be challenging when fine temporal resolution is required (time step below 100-200ns). In the recent years, our research group has proposed various methods to simulate in real-time PEPDS using FPGAs and time step as small as 50ns. While the proposed methods allow achieving the desired temporal resolution, they are extremely demanding in terms of resources usage and the size of the PEPDS that can be simulated on a single FPGA is strongly limited. In this dissertation -work that takes as an example application the US Navy electric Ship Zonal System (SZS)- a platform based on a commercial CPU based simulator and on a custom multi-FPGA simulator is presented. The multi-FPGA simulator enables system level PEPDS analysis while maintaining a very small-time step (70ns). Using a CPU commercial platform and multi rate execution, the power electronics part of the system is simulated together with the slow electro-mechanical portion of the PEPDS maintaining a unified vision. To achieve such a small simulation time step, the LBLMC method is applied and an innovative parallel bus interface architecture for a three FPGAs layout is introduced. The PEPDS model is decomposed for multi-FPGA executions using the nodal decomposition method. Two converters models, MMC and DAB, have been developed and included in the Open Real-Time Simulation (ORTiS) framework. To allow multi-rate execution a dedicated software and hardware interface has been developed so to interface the custom FPGA based simulator -operating with a 70ns time step- with the commercial CPU based simulator -operating at 25μs. Furthermore, to increase the flexibility and scalability of the proposed simulation platforms, a co-simulation interface based on the Aurora protocol and realizing communication between a multi-CPU and a multi-FPGA based platforms is introduced