Conventional fault-tolerance approaches for Networks-on-Chip (NoCs) cannot be applied to high dependability systems due to their different goals and constraints. These systems impose strict integrity, resilience and real-time requirements. In order to meet these requirements, all possible effects of random hardware errors must be taken into account, silent data corruption must be prevented and the resulting system must be predictable in the presence of errors. In this paper, we present a wormhole-switched NoC with virtual channels for high dependability systems hardened against soft errors. The NoC is developed based on results of a Failure Mode and Effects Analysis. It efficiently handles errors in different network layers and operate...
Puttmann C, Porrmann M, Rückert U. Extending GigaNoC towards a Dependable Network-on-Chip. In: Dige...
A fault-tolerant adaptive wormhole routing function for Networks-on-Chips (NoCs) is presented. The n...
Rapid scaling of transistor gate sizes has increased the density of on-chip integration and paved th...
The aggressive semiconductor technology scaling provides the means for doubling the amount of transi...
The aggressive semiconductor technology scaling provides the means for doubling the amount of transi...
The advent of deep sub-micron technology has exacerbated reliability issues in on-chip interconnects...
Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of proces...
Networks-on-Chip (NoCs) appeared as a strategy to deal with the communication requirements of comple...
Networks-on-Chip (NoCs) appeared as a strategy to deal with the communication requirements of comple...
Network-on-Chip (NoC) is a key component in chip multiprocessors (CMPs) as it supports communication...
Networks-on-Chip (NoCs) appeared as a strategy to deal with the communication requirements of comple...
Networks-on-Chip (NoCs) appeared as a strategy to deal with the communication requirements of comple...
A fault-tolerant adaptive wormhole routing function for Networks-on-Chips (NoCs) is presented. The n...
International audienceThree-dimensional Networks-on-Chips (3D-NoCs) have emerged as an alternative t...
International audienceThree-dimensional Networks-on-Chips (3D-NoCs) have emerged as an alternative t...
Puttmann C, Porrmann M, Rückert U. Extending GigaNoC towards a Dependable Network-on-Chip. In: Dige...
A fault-tolerant adaptive wormhole routing function for Networks-on-Chips (NoCs) is presented. The n...
Rapid scaling of transistor gate sizes has increased the density of on-chip integration and paved th...
The aggressive semiconductor technology scaling provides the means for doubling the amount of transi...
The aggressive semiconductor technology scaling provides the means for doubling the amount of transi...
The advent of deep sub-micron technology has exacerbated reliability issues in on-chip interconnects...
Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of proces...
Networks-on-Chip (NoCs) appeared as a strategy to deal with the communication requirements of comple...
Networks-on-Chip (NoCs) appeared as a strategy to deal with the communication requirements of comple...
Network-on-Chip (NoC) is a key component in chip multiprocessors (CMPs) as it supports communication...
Networks-on-Chip (NoCs) appeared as a strategy to deal with the communication requirements of comple...
Networks-on-Chip (NoCs) appeared as a strategy to deal with the communication requirements of comple...
A fault-tolerant adaptive wormhole routing function for Networks-on-Chips (NoCs) is presented. The n...
International audienceThree-dimensional Networks-on-Chips (3D-NoCs) have emerged as an alternative t...
International audienceThree-dimensional Networks-on-Chips (3D-NoCs) have emerged as an alternative t...
Puttmann C, Porrmann M, Rückert U. Extending GigaNoC towards a Dependable Network-on-Chip. In: Dige...
A fault-tolerant adaptive wormhole routing function for Networks-on-Chips (NoCs) is presented. The n...
Rapid scaling of transistor gate sizes has increased the density of on-chip integration and paved th...