Performance Analysis of SRAM Designs Using TSMC 90nm CMOS TECHNOLOGY

Cache memory, which is built up of static-random-access-memory (SRAM) cells, is an important part in computer aiming to reduce latency caused by the separation of processor and external memory. Designing of SRAM must consider stability in operation of holding, writing, and reading. This study analyses and shows advantages in using eight-transistor (8T) structure in compared with normal six-transistor (6T) one for the SRAM cell. The 8T structure occupies a small area while significantly enhancing the stability. The operation of the 32-bit memory based on the 90nm complementary metal oxide semiconductor (CMOS) technology is described in detailed by using the CADENCE SPECTRE tool. Additionally, this study analyses and compares the power consumption, the delays in reading and writing operations of each structure under various simulated scenarios