Half Diagonal Matrix Codes for Reliable Embedded Memories

Reliability of embedded memories is dependent on at-speed rated correction capability of error detection and correction codes. Many critical applications like medical databases, rocket launch details stored in memories require accurate data and which cause major human losses or economy losses even if a 1% of data is compromised. This paper focuses on developing improved reliable error detection and correction codes with minimum redundant bits and maximum code rate. The decoder uses the concept of Encoder Reuse Technique along with the Modulo-2 addition to calculate syndrome, error location and correction of data bits when data is read from memory. The codes are represented in verilog hardware description language and simulated in the Tool Xilinx ISE 14.5 for XC7Z020-1CLG484 FPGA. The codes are evaluated for their performance in terms of technology parameters like area, delay, power, power – delay product, etc. Also for other parameters like bit overhead, code rate, code efficiency, correction coverage, correction efficiency, etc and correction coverage per cost for combined evaluation. The implemented half diagonal code is more effective as compared to existing matrix codes, it reduces bit overhead at least by 5.5% to 46.96% and coding rate increased at least by 16.74% to 23.85%