We present deterministic upper and lower bounds on the slowdown required to simulate an (n;m)- PRAM on a variety of networks. The upper bounds are based on a novel scheme that exploits the splitting and combining of messages. This scheme can be implemented on an n-node d-dimensional mesh (for constant d) and on an n-leaf pruned butterfly and attains the smallest worst-case slowdown to date for such interconnections, namely, O(n1=d (log(m=n))1\ua11=d ) for the d-dimensional mesh (with constant d) and O(pn log(m=n)) for the pruned butterfly. In fact, the simulation on the pruned butterfly is the first PRAM simulation scheme on an area-universal network. Finally, we prove restricted and unrestricted lower bounds on the slowdown of any determin...
Abstract. The power of shared-memory in models of parallel computation is studied, and a novel distr...
Andrews introduced a number of techniques for automaticallyhiding latency when performing simulation...
We present efficient emulations of the CRCW PRAM on a large class of processor interconnection netwo...
We present deterministic upper and lower bounds on the slowdown required to simulate an (n;m)- PRAM ...
AbstractWe present deterministic upper and lower bounds on the slowdown required to simulate an (n, ...
We present deterministic upper and lower bounds on the slowdown required to simulate an (n,m)-PRAM o...
AbstractWe show a lower bound of Ω(min{log m, √n}) on the slowdown of any deterministic emulation of...
This paper describes a scheme to implement a shared address space of size m on an n-node mesh, with ...
This paper describes an improved scheme for PRAM simulation on the mesh. The simulation algorithm ac...
We present a constructive deterministic simulation of a PRAM with n processors and m = n^alpha; shar...
The Parallel Random Access Machine (PRAM) is an abstract parallel machine consisting of a synchrono...
AbstractWe consider randomized simulations of shared memory on a distributed memory machine (DMM) wh...
A parallel processor network is called n-universal with slowdown s, if it can simulate each computat...
A deterministic scheme for the simulation of (n, m)-PRAM computation is devised. Each PRAM step is s...
The problem of simulating a PRAM with $n$ processors and memory size $m \geq n$ on an $n$-node boun...
Abstract. The power of shared-memory in models of parallel computation is studied, and a novel distr...
Andrews introduced a number of techniques for automaticallyhiding latency when performing simulation...
We present efficient emulations of the CRCW PRAM on a large class of processor interconnection netwo...
We present deterministic upper and lower bounds on the slowdown required to simulate an (n;m)- PRAM ...
AbstractWe present deterministic upper and lower bounds on the slowdown required to simulate an (n, ...
We present deterministic upper and lower bounds on the slowdown required to simulate an (n,m)-PRAM o...
AbstractWe show a lower bound of Ω(min{log m, √n}) on the slowdown of any deterministic emulation of...
This paper describes a scheme to implement a shared address space of size m on an n-node mesh, with ...
This paper describes an improved scheme for PRAM simulation on the mesh. The simulation algorithm ac...
We present a constructive deterministic simulation of a PRAM with n processors and m = n^alpha; shar...
The Parallel Random Access Machine (PRAM) is an abstract parallel machine consisting of a synchrono...
AbstractWe consider randomized simulations of shared memory on a distributed memory machine (DMM) wh...
A parallel processor network is called n-universal with slowdown s, if it can simulate each computat...
A deterministic scheme for the simulation of (n, m)-PRAM computation is devised. Each PRAM step is s...
The problem of simulating a PRAM with $n$ processors and memory size $m \geq n$ on an $n$-node boun...
Abstract. The power of shared-memory in models of parallel computation is studied, and a novel distr...
Andrews introduced a number of techniques for automaticallyhiding latency when performing simulation...
We present efficient emulations of the CRCW PRAM on a large class of processor interconnection netwo...