International audienceWe report on the realisation of a 6:834 GHz synthesis chain for the Trapped Atom Clock on a Chip (TACC) that is being developed at LNE-SYRTE. The stability of the chain is 10<sup>-14</sup> at 1 s, one order of magnitude below the stability goal of TACC. This ensures that the synthesizer will not be a limiting factor of the clock performance. The chain is based on the frequency multiplication of a 100 MHz reference signal to 6:4 GHz. It uses a comb generator based on a monolithic GaAs non-linear transmission line. This is a novelty in the fabrication of high stability microwave synthesisers
Following our earlier work, on a new approach to synthesising the Cs hyperfine frequency of 9.192 GH...
This paper presents a low-power first-order frequency synthesizer architecture suitable for high-spe...
Date of publication November 8, 2016; date of current version May 10, 2017.In this paper, we report ...
International audienceWe report on the realisation of a 6:834 GHz synthesis chain for the Trapped At...
Abstract Phase noise of the frequency synthesizer is one of the main limitations to the short‐term s...
International audienceThis paper presents the development of a 9.192 GHz microwave frequency synthes...
International audienceWe report the development, absolute phase noise, and residual phase noise char...
We report on the development and characterization of novel 4.596 GHz and 6.834 GHz microwave freque...
We present a low phase noise microwave frequency synthesizer for the integrating sphere cold atom cl...
The Dick effect is one of the main factors limiting the short-term frequency stability of Cs fountai...
221-227The performance of newer generations of ultra high stability atomic frequency standards base...
In this letter, the design of a low phase noise frequency synthesizer is presented. The synthesizer ...
International audienceThis paper describes a 4.596 GHz frequency synthesis based on a 2.1 GHz solid ...
A PLL has been designed for high frequency clock generation with only 280 fs RMS jitter. The integer...
In this paper, we present the design, fabrication, and electrical characterization of a low-power mi...
Following our earlier work, on a new approach to synthesising the Cs hyperfine frequency of 9.192 GH...
This paper presents a low-power first-order frequency synthesizer architecture suitable for high-spe...
Date of publication November 8, 2016; date of current version May 10, 2017.In this paper, we report ...
International audienceWe report on the realisation of a 6:834 GHz synthesis chain for the Trapped At...
Abstract Phase noise of the frequency synthesizer is one of the main limitations to the short‐term s...
International audienceThis paper presents the development of a 9.192 GHz microwave frequency synthes...
International audienceWe report the development, absolute phase noise, and residual phase noise char...
We report on the development and characterization of novel 4.596 GHz and 6.834 GHz microwave freque...
We present a low phase noise microwave frequency synthesizer for the integrating sphere cold atom cl...
The Dick effect is one of the main factors limiting the short-term frequency stability of Cs fountai...
221-227The performance of newer generations of ultra high stability atomic frequency standards base...
In this letter, the design of a low phase noise frequency synthesizer is presented. The synthesizer ...
International audienceThis paper describes a 4.596 GHz frequency synthesis based on a 2.1 GHz solid ...
A PLL has been designed for high frequency clock generation with only 280 fs RMS jitter. The integer...
In this paper, we present the design, fabrication, and electrical characterization of a low-power mi...
Following our earlier work, on a new approach to synthesising the Cs hyperfine frequency of 9.192 GH...
This paper presents a low-power first-order frequency synthesizer architecture suitable for high-spe...
Date of publication November 8, 2016; date of current version May 10, 2017.In this paper, we report ...