Resource modeling of mmwave transceivers for wireless communications at the chip scale

Wireless Network-on-Chip (WNoC), where communications takes place at the chip scale between integrated antennas and transceivers and using the chip package as propagation medium, shows promise in addressing the challenges of wireline Network-on-Chip (NoC) in modern multicore processors. Two of the most important aspects of this new paradigm are area and power consumption, which are heavily limited by the evident constraints of the chip scenario. Hence, to understand the value of the WNoC idea, it is imperative to have area and power models of the transceivers used in the communication. Such models, however, are largely missing because RF designers are typically bound to a strict set of specifications relative to the frequency band or output power, among others, in stark contrast to the WNoC scenario which does not impose such limitations. In this context, the present thesis lays down the first steps towards the modeling of wireless transceivers for WNoC communication using a bottom-up approach, component by component, using (i) known design rules, (ii) existing surveys for certain subsystems such as the data converters or power amplifiers, and (iii) relevant specific designs from the literature. The developed models allow to sweep key input parameters such as the frequency, the channel losses, the modulation rate for two low-order modulations, OOK and QPSK, paving the way to the exploration of WNoC architectures for future multicore processing systems