Nowadays, high-performance microprocessors are demanded in many fields, including those with high-reliability requirements. Commercial microprocessors present a good tradeoff between cost, size, and performance, albeit they must be adapted to satisfy the reliability requirements when they are used in harsh environments. This work presents a high-end multiprocessor hardened with macrosynchronized lockstep and additional protections. A commercial dual-core Advanced RISC Machine (ARM) cortex A9 has been used as a case study and a complete hardened system has been developed. Evaluation of the proposed hardened system has been accomplished with exhaustive fault injection campaigns and proton irradiation. The hardening approach has been accomplis...
This paper describes a SRAM designed for space and nuclear physics applications. The device has been...
The interest of the space industry in Real-Time Operating Systems for achieving stringent real-time...
Multigigabit serial links implemented by means of static random access memory (SRAM)-based field-pro...
Nowadays, high-performance microprocessors are demanded in many fields, including those with high-re...
All-Programmable System-on-Chips (APSoCs) constitute a compelling option for employing applications ...
In various fields, such as those with high-reliability requirements, there is a growing demand for h...
Proceeding of: 32th European Symposium on Reliability of Electron Devices, Failure Physics and Analy...
This paper presents a new concept of building a high performance, radiation hardened computer from C...
This work presents the evaluation of a new dualcore lockstep hybrid approach aimed to improve the fa...
A high-level C++ hardening library is designed for the protection of critical software against the h...
The embedded processors operating in safety- or mission-critical systems are not allowed to fail. An...
This article presents Lock-V, a heterogeneous fault tolerance architecture that explores a dual-core...
The aggressive scaling of semiconductor devices has caused a significant increase in the soft error ...
Soft errors are one of the significant design technology challenges at smaller technology nodes and ...
This paper describes a SRAM designed for space and nuclear physics applications. The device has been...
This paper describes a SRAM designed for space and nuclear physics applications. The device has been...
The interest of the space industry in Real-Time Operating Systems for achieving stringent real-time...
Multigigabit serial links implemented by means of static random access memory (SRAM)-based field-pro...
Nowadays, high-performance microprocessors are demanded in many fields, including those with high-re...
All-Programmable System-on-Chips (APSoCs) constitute a compelling option for employing applications ...
In various fields, such as those with high-reliability requirements, there is a growing demand for h...
Proceeding of: 32th European Symposium on Reliability of Electron Devices, Failure Physics and Analy...
This paper presents a new concept of building a high performance, radiation hardened computer from C...
This work presents the evaluation of a new dualcore lockstep hybrid approach aimed to improve the fa...
A high-level C++ hardening library is designed for the protection of critical software against the h...
The embedded processors operating in safety- or mission-critical systems are not allowed to fail. An...
This article presents Lock-V, a heterogeneous fault tolerance architecture that explores a dual-core...
The aggressive scaling of semiconductor devices has caused a significant increase in the soft error ...
Soft errors are one of the significant design technology challenges at smaller technology nodes and ...
This paper describes a SRAM designed for space and nuclear physics applications. The device has been...
This paper describes a SRAM designed for space and nuclear physics applications. The device has been...
The interest of the space industry in Real-Time Operating Systems for achieving stringent real-time...
Multigigabit serial links implemented by means of static random access memory (SRAM)-based field-pro...