Using Adaptive Body Biasing for Robust Process Variation Aware DRAM Design

Large dense structures like DRAMs are particularly susceptible to process variation, which can lead to variable latencies in different memory arrays. However, very little work exists on variation studies in the DRAM as DRAMs were traditionally placed off-chip limiting their latency impact on the overall processor performance. However, emerging technology trends like three dimensional integration, sophisticated memory controllers substantially reduces DRAM access latency. This makes process variation a critical upcoming challenge in DRAMs that must be addressed in current and forthcoming technology generations. In this paper, we propose a unique adaptive body biasing algorithm for designing large DRAMs robust to process variation. WE propose a hierarchical and computationally efficient framework by combining cell level Hspice models with sensitivity based models for statistical timing analysis. We report an average of 14.66% improvement in the DRAM yield on 1GB DRAM array. To the best of our knowledge, ours is the first technique to model the impact of process variation on large scale DRAM arrays. Copyright © 2013 American Scientific Publishers