Negative Capacitance Field-Effect Transistor Design and Machine Learning Applications in Compact Models

With the scaling of the transistor, fabrication of an actual device and modeling of an ultra-short channel transistor becomes more and more challenging. Dr. Salahuddin proposed a negative capacitance field-effect transistor (NCFET) in 2008. By utilizing the ferroelectric negative capacitance region with proper capacitance matching a ferroelectric layer with a dielectric layer, the overall effective oxide thickness could be further thinned down without affecting much of the carrier mobility.A technique of optimization of an NCFET will be proposed in chapter 2. By utilizing process techniques like mask oxidation, a non-uniform interfacial layer can be formed to create a more uniform metal-oxide-semiconductor capacitance along the channel (Cmos). The overall capacitance matching of an NCFET can be improved because of a uniform Cmos profile. Chapter 3 will introduce a simulation scheme of NCFETs variation due to dielectric grains within a ferroelectric film. This scheme can be applied to the future estimation of NCFETs variation given the grains' size and the ferroelectric parameters. The effect and compact modeling of the polarization gradient effect will be demonstrated in Chapter 4. With the feature of polarization gradient effect in an NCFET compact model, the characteristics of an NCFET can be better captured, such as negative drain resistance and negative drain-induce barrier 2 effect (DIBL). Energy analysis of an NCFET will be presented in Chapter 5. The consistency between TCAD energy calculation by the integral over the grids with the Landau equation and power consumption calculation from the circuit is shown in detail. Negative capacitance benefits on FinFET and gate-all-around (GAA) FET will be presented in chapters 6 & 7, respectively. Baseline devices of a FinFET and a GAAFET are made in technology computer-aided design (TCAD) and are calibrated to International Roadmap for Devices and Systems (IRDS) tables. NC parameters are also extracted from an experiment on metal-oxide-semiconductor capacitance (MOSCAP). How many nodes NC extends the baseline will be discussed. A compact model of an anti-ferroelectric on an NCFET will be presented in Chapter 8. Potential applications of machine learning will be illustrated in Chapters 9 & 10. Machine learning-assisted parameter extraction will be presented in Chapter 9. In the long run, using machine learning-assisted models as an alternative to the conventional equation-based compact models will be shown in Chapter 10. In the end, Chapter 11 will conclude chapters and propose some future work