A new BIST scheme for on-chip testing of non-volatile memories and based on signature analysis is presented. The signature of the whole memory, whose content can be changed selectively by the user, is dynamically self-learned by the memory and it is saved in a dedicated memory location. Either such a signature can be externally compared with the expected one in order to check for the programming operation, or it can be used for comparison purposes when data retention must be self-tested
Memory built-in self-test (BIST) is a widely used technique to allow the self-test and self-checking...
ISBN 0-7803-9038-5International audienceIn modern SoCs embedded memories include the large majority ...
ISBN 978-1-4577-1053-7International audienceIn modern SoCs embedded memories concentrate the majorit...
A new BIST scheme for on-chip testing of non-volatile memories and based on signature analysis is p...
A new BIST scheme suitable for on-chip testing of non-volatile memories and based on signature analy...
The design and architecture of a reconfigurable memory BIST unit is presented. The proposed memory B...
Abstract—Memory is increasingly important because of the high density of current memory chips. W...
[[abstract]]© 2001 Institute of Electrical and Electronics Engineers -We present a processor-program...
Abstract—As there are increasing functionalities in modern system-on-chip (SOC) design, the amount o...
Chip functionality testing can greatly benefit from a Built In Self-Test (BIST). The Self-Test Using...
[[abstract]]In the present invention a built in self test (BIST) for an embedded memory is described...
The authors analyse off-chip and on-chip signature checking schemes suitable for boundary scan (BS) ...
Testing VLSI circuits is a complex task that requires enormous amounts of resources. To decrease tes...
Testing digital devices constitutes a major portion of the cost and effort involved in their design,...
ISBN: 0780321022Signature analyzers are very efficient output response compactors in BIST techniques...
Memory built-in self-test (BIST) is a widely used technique to allow the self-test and self-checking...
ISBN 0-7803-9038-5International audienceIn modern SoCs embedded memories include the large majority ...
ISBN 978-1-4577-1053-7International audienceIn modern SoCs embedded memories concentrate the majorit...
A new BIST scheme for on-chip testing of non-volatile memories and based on signature analysis is p...
A new BIST scheme suitable for on-chip testing of non-volatile memories and based on signature analy...
The design and architecture of a reconfigurable memory BIST unit is presented. The proposed memory B...
Abstract—Memory is increasingly important because of the high density of current memory chips. W...
[[abstract]]© 2001 Institute of Electrical and Electronics Engineers -We present a processor-program...
Abstract—As there are increasing functionalities in modern system-on-chip (SOC) design, the amount o...
Chip functionality testing can greatly benefit from a Built In Self-Test (BIST). The Self-Test Using...
[[abstract]]In the present invention a built in self test (BIST) for an embedded memory is described...
The authors analyse off-chip and on-chip signature checking schemes suitable for boundary scan (BS) ...
Testing VLSI circuits is a complex task that requires enormous amounts of resources. To decrease tes...
Testing digital devices constitutes a major portion of the cost and effort involved in their design,...
ISBN: 0780321022Signature analyzers are very efficient output response compactors in BIST techniques...
Memory built-in self-test (BIST) is a widely used technique to allow the self-test and self-checking...
ISBN 0-7803-9038-5International audienceIn modern SoCs embedded memories include the large majority ...
ISBN 978-1-4577-1053-7International audienceIn modern SoCs embedded memories concentrate the majorit...