Novel Algorithms and Hardware Architectures for Computational Subsystems Used in Cryptography and Error Correction Coding

A modified, single error-correcting, and double error detecting Hamming code, hereafter referred to as modified SEC-DED Hamming code, is proposed in this research. The code requires fewer logic gates to implement than the SEC-DED Hamming code. Also, unlike the popular Hsiao's code, the proposed code can determine the error in the received word from its syndrome location in the parity check matrix. A detailed analysis of the area and power utilization by the encoder and decoder circuits of the modified SEC-DED Hamming code is also discussed. Results demonstrate that this code is an excellent alternative to Hsiao's code as the area and power values are very similar. In addition, the ability to locate the error in the received word from its syndrome is also of particular interest. Primitive polynomials play a crucial role in the hardware realizations for error-correcting codes. This research describes an implementation of a scalable primitive polynomial circuit with coefficients in GF(2). The standard cell area and power values for various degrees of the circuit are analyzed. The physical design of a degree 6 primitive polynomial computation circuit is also provided. In addition to the codes, a background of the already existing SPX GCD computation algorithm is provided. Its implementation revealed that the combinational implementation of the SPX algorithm utilizes a significantly lesser area than Euclid's algorithm. The FSMD implementation of the SPX algorithm reduces both dynamic and leakage power consumption. The physical design of the GCD computation using the SPX algorithm is also provided