Layout dependence of CMOS Latch-up

This paper presents a detailed analysis of CMOS latchup dependencies on layout and geometrical dimensions. To this purpose test structures have been fabricated featuring butted contacts and guard rings with different values of critical distances. The devices have been experimentally characterized in the triggering and sustaining regime, and numerical simulations have been extensively used to interpret the experimental data. It is shown that great care should be taken in designing protection structures since larger areas do not always lead to enhanced latchup immunity