This paper presents a 7-bit digital to phase converter (DPC) for high speed clock and data recovery (CDR) applications which is capable of generating multi-phase clocks at 7-GHz frequency. Fabricated in a standard 65-nm CMOS technology, the design introduces a modified phase interpolator (PI) and a quadrature phase corrector (QPC) to reduce the effect of the circuit imperfections on the DPC's resolution and linearity. Employing a 14-GHz quadrature reference clock, the DPC achieves DNL/INL of 0.7/6 LSB respectively while consuming 40.5 mW power from 1.05 V supply
The demand for wireless communication, mobile computing and multifunctional portable electronics has...
This thesis presents the design and implementation of a CDR with 'phase reset.' By continually 'rese...
This paper presents a time-to-digital converter (TDC) architecture capable of reaching high-precisio...
This paper presents a 7-bit digital to phase converter (DPC) for high speed clock and data recovery ...
A 10GHz analog phase interpolator (PI) in Global Foundry 65nm CMOS technology has been presented. Th...
With a new 1/8-rate linear phase detector (PD), a 5-Gbit/s clock and data recovery (CDR) circuit is ...
A Gb/s clock and data recovery (CDR) circuit using 1/4th-rate digital quadricorrelator frequency det...
A clock and data recovery (CDR) circuit for 1.5-5.0 Gb/s wireline transceiver is described. A phase ...
This work presents a low-power low-cost CDR design for RapidIO SerDes. The design is based on phase ...
In this brief, a 1/10-rate bang-bang phase detector (BBPD) using a single edge-tracking clock and a ...
A 6-Gbps dual-mode digital clock and data recovery (CDR) circuit for both the mesochronous clocking ...
Figure 1. Block diagram of a conventional digitally-controlled dual-loop CDR Abstract- A novel 1.25G...
A referenceless digital clock and data recovery (D-CDR) circuit using a half-rate jitter-tolerant fr...
High-speed data transmission through wireline links, either copper or optical based, has become the ...
This paper presents a monolithically integrated clock and data recovery (CDR) circuit with 1:2 demul...
The demand for wireless communication, mobile computing and multifunctional portable electronics has...
This thesis presents the design and implementation of a CDR with 'phase reset.' By continually 'rese...
This paper presents a time-to-digital converter (TDC) architecture capable of reaching high-precisio...
This paper presents a 7-bit digital to phase converter (DPC) for high speed clock and data recovery ...
A 10GHz analog phase interpolator (PI) in Global Foundry 65nm CMOS technology has been presented. Th...
With a new 1/8-rate linear phase detector (PD), a 5-Gbit/s clock and data recovery (CDR) circuit is ...
A Gb/s clock and data recovery (CDR) circuit using 1/4th-rate digital quadricorrelator frequency det...
A clock and data recovery (CDR) circuit for 1.5-5.0 Gb/s wireline transceiver is described. A phase ...
This work presents a low-power low-cost CDR design for RapidIO SerDes. The design is based on phase ...
In this brief, a 1/10-rate bang-bang phase detector (BBPD) using a single edge-tracking clock and a ...
A 6-Gbps dual-mode digital clock and data recovery (CDR) circuit for both the mesochronous clocking ...
Figure 1. Block diagram of a conventional digitally-controlled dual-loop CDR Abstract- A novel 1.25G...
A referenceless digital clock and data recovery (D-CDR) circuit using a half-rate jitter-tolerant fr...
High-speed data transmission through wireline links, either copper or optical based, has become the ...
This paper presents a monolithically integrated clock and data recovery (CDR) circuit with 1:2 demul...
The demand for wireless communication, mobile computing and multifunctional portable electronics has...
This thesis presents the design and implementation of a CDR with 'phase reset.' By continually 'rese...
This paper presents a time-to-digital converter (TDC) architecture capable of reaching high-precisio...