Optimization and Comparison of High Performance and Low Power NOR Gate Circuit Using Hybrid Model of Dynamic Voltage Scaling and MTCMOS Technique

The strategy joins VS (Voltage Scaling) and MTCMOS procedure that aids in lessening active and passive power dissemination separately deprived of corrupting the circuit’s execution. The anticipated procedure set aside power dispersal by 35% to 85% when contrasted with regular CMOS and other existing procedures and the numbers of transistors is reduced in existing circuit to reduce the overall energy consumption as well as the reduced transistor logic is area efficient and comparison is done with existing design and NMOS structure. A 2-terminal input NOR gate is executed utilizing the VS-MTCMOS procedure in sub-edge district throughout various ranges of temperature at different voltage level. Electronic Design Automation Tool is utilized in the direction of reproduce the planned circuit. As convenience of electronic frameworks requires longer battery life, it is important that they should have instruments in spot to diminish the force utilization. One of the methods used to build power productivity at the framework level is Dynamic Voltage and Frequency Scaling (DVFS). CMOS rationale is broadly utilized in VLSI circuits yet because of scrambling of innovation, limit voltage of the semiconductors utilized in CMOS circuits decline, results in increment in spillage power. Active power utilization, that is relative to source potential difference (VDD)2 auxiliary combined to general power dispersal. This outcomes in short battery lifespan of cell phones. Transitory is a clever strategy in the direction of shorten mutually unique power dissemination furthermore, spillage power. © 2022, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd