Exploring FPGA dynamic reconfigurability on a RISC-V based System-on-Chip featuring a Soft General Purpose Processing Unit

General Purpose Computing on Graphical Processing Units has been exploited in many different fields for years. The hardware architectures enabling this kind of computations are increasingly complex. Their use in on-the-edge applications is often limited by the limited resources, in terms of space and power, that characterize the systems involved. Exploiting dynamic partial reconfiguration of Field Programmable Gate Array devices makes a system able to specialize part of its architecture through faster reconfiguration cycles without disabling the rest of the system. Additionally, dynamic partial reconfiguration enables the creation of advanced heterogeneous Computing systems with better Programmabel Logic (PL) utilization and Power Consumption. Regarding soft-GPU, their performance and resource usage can be tuned accordingly to the application requirements, making their use extremely flexible. We take into consideration a set of alternatives, both provided by Xilinx and from literature, to manage and make use of Dynamic Reconfiguration. In this work, we explore a set of partial reconfiguration functionalities applied to a soft-GPU and the impact on the performances of the entire systems. Several system configurations have been explored. PCAP and ICAP interfaces, used in Xilinx's FPGAs, enable dynamic Partial Reconfiguration in such systems. PCAP is only present in SoC and MPSoC FPGAs, can only be accessed by the pre-embedded ARM core that also implements all the hardware to correctly manage the interface. Conversely, ICAP is present in all Xilinx's FPGA and can be accessed both by the ARM Core or directly within the Programmable Logic, however, additional components must be employed as a mean to correctly manage the interface. These components are generally called "Partial Reconfiguration Controllers". Several controllers have been tested and in different configurations, both from Xilinx and from literature, to test their performances. As a test-case, we have taken into consideration the usage of the ICU4SAT system, a System-on-Chip created for space applications composed of open source components, then we implemented partial reconfiguration functionalities on it. This system, makes use of a General Purpose Soft-GPU (a Graphical Processing Unit implemented on top of the PL), as a mean to enable hardware-acceleration for highly-parallelizable tasks. In the context of space missions several different tools, that can take advantage of such GPU, are necessary: image and video processing, mathematical tools, machine learning and so on. Four different configurations of the soft-GPU have been implemented, each one with increasing computational power. Dynamic Partial Reconfiguration enables the possibility to reprogram the GPU with a different configuration to adapt the computational power to that needed by the task with the result of less dynamic power consumption. An OpenCL implementation of the sobel filter has been used to assess the performances of the system