Real-time Data analysis at LHCb with heterogeneous computing achitectures

The LHCb Experiment is a dedicated Flavor-physics experiment at the LHC at CERN, and will soon start its next physics run (Run-3) at a luminosity of 2X10^33 cm$^-2s^-1, that is five times higher than in previous runs. During Run~3, the LHCb trigger will, for the first time, perform a complete reconstruction of all events at the full LHC crossing rate of 30 MHz. This, in conjunction with the low-momentum thresholds needed for Flavor physics, represents a major computing challenge, that LHCb is meeting with the deployment a large CPU array for event reconstruction, and a GPU array for the first stage of the High Level Trigger (HLT1). While the Run-3 data acquisition system of LHCb is stretching the state of the art of real-time computing, the Collaboration is already planning for a further detector upgrade, aimed at taking data at even larger luminosities (a further factor five above Run-3), for a data taking period that will last until the conclusion of the LHC program. For this future runs, the hope for being able to take data in an effective way, rests on the introduction of more powerful, innovative, heterogeneous computing solutions capable of real-time processing of data flows at the level of approximately 200 Terabits/s. One solution currently under development is a FPGA-based, highly-parallelized custom tracking processor, capable of performing real-time reconstruction of particle tracks in a more efficient way than it is possible with any traditional CPU or GPU architectures. This will be built using the so-called "Artificial Retina" architecture, that exploits to its fullest extent the FPGA computational and bandwidth capabilities, by distributing the processing of each event over an array of electronic boards, interconnected by a high-bandwidth optical network. A system with this level of performance can be integrated in the DAQ chain of the experiment, and reduce the computational load of the High Level Trigger to a manageable level, operating in a transparent way during data readout. After a few years of R&D on smaller prototypes, a first life-size prototype of this system is being built, to develop and demonstrate the viability of the technology in realistic data-taking conditions. This demonstrator, funded and supported by INFN, will be installed in a special Coprocessor Testbed facility located at CERN, that LHCb has established for the specific purpose of testing new solutions for data acquisition in realistic conditions with real experiment data. The project is aimed at processing data in real-time from a significant portion (1/4) of the new VELO pixel detector, which is the primary tracking detector of LHCb, detecting charged particles in the region closest to the interaction point, with a spatial resolution sufficient to cleanly distinguish the decay lenghts of weakly--decaying b-and c-hadrons. The VELO is the first detector that needs to be processed as the start of the reconstruction sequence of the complete event in LHCb, and currently uses up almost a half of the available computing resources, making it a very significant benchmark test for a new processor. The future upgrades of this detector, that are likely to include the measurement of time information, will pose an even greater reconstruction challenge. This thesis describes the steps involved in building the demonstrator and commissioning it at the LHCb Coprocessor Testbed, where it is expected to start operations in summer 2022. The first chapter describes the LHCb Experiment structure for the the Run-3. The second Chapter introduces the principles of the "Artificial Retina" architecture, describing its concepts and structure, and its general principles of implementation. The third chapter discusses the actual implementation details in commercially available digital devices, and the methodology for its integration in the LHCb data acquisition system. The fourth chapter describes in detail the structure of the FPGA demonstrator for Run 3. The fifth chapter discusses the communication firmware, the internal high-speed optical data distribution network, and the process of its testing and commissioning. The sixth and last chapter describes the development and test of the core firmware of the demonstrator, that performs the actual pattern recognition of tracks in the VELO detector. This firmware is designed to exploit the logic resources and internal DSPs of state-of-the art FPGA devices to achieve the extreme level of parallelism needed to provide the throughput performance that LHCb will require for its future physics goals