We present a simple test structure (derived from the CBCM technique proposed by Sylvester et al.) that enables the selective extraction of cross-coupling capacitance between arbitrary on-chip interconnects. We discuss the silicon implementation on a 0.18um CMOS process and report preliminary experimental result
This thesis describes the theory, simulation and experimental implementation of a method by which an...
The experimental characterization of gate capacitance in nanoscale devices is challenging. We report...
This paper proposes a novel charge-based Complementary Metal Oxide Semiconductor (CMOS) capacitive s...
We present a simple test structure (derived from the CBCM technique proposed by Sylvester et al.) th...
Geometry scaling increases the relative effect of coupling capacitances on performance, power, and n...
Charge-based capacitance measurements (CBCMs) are widely used to estimate on-chip wiring capacitance...
[[abstract]]In this letter, charge-based capacitance measurement (CBCM) is applied to characterize b...
[[abstract]]In this work, we describe a novel operation of charge-injection-induced error-free charg...
Interconnection parasitic capacitance is the dominant delay and noise source in modern integrated ci...
Interconnection parasitic capacitance is the dominant delay and noise source in modem integrated cir...
The measurement of capacitance by Charge Based Capacitor Measurement (CBCM) is the most widely used ...
A method and a relative test structure for measuring the coupling capacitance between two interconne...
The paper deals with a modified CBCM (Charge-Based Capacitance Measurements) method for nonlinear ca...
technical reportA novel approach to solving the accurate capacitance and resistance extraction probl...
Single-level and multi-path interconnect structures embedded in dielectrics on a silicon substrate a...
This thesis describes the theory, simulation and experimental implementation of a method by which an...
The experimental characterization of gate capacitance in nanoscale devices is challenging. We report...
This paper proposes a novel charge-based Complementary Metal Oxide Semiconductor (CMOS) capacitive s...
We present a simple test structure (derived from the CBCM technique proposed by Sylvester et al.) th...
Geometry scaling increases the relative effect of coupling capacitances on performance, power, and n...
Charge-based capacitance measurements (CBCMs) are widely used to estimate on-chip wiring capacitance...
[[abstract]]In this letter, charge-based capacitance measurement (CBCM) is applied to characterize b...
[[abstract]]In this work, we describe a novel operation of charge-injection-induced error-free charg...
Interconnection parasitic capacitance is the dominant delay and noise source in modern integrated ci...
Interconnection parasitic capacitance is the dominant delay and noise source in modem integrated cir...
The measurement of capacitance by Charge Based Capacitor Measurement (CBCM) is the most widely used ...
A method and a relative test structure for measuring the coupling capacitance between two interconne...
The paper deals with a modified CBCM (Charge-Based Capacitance Measurements) method for nonlinear ca...
technical reportA novel approach to solving the accurate capacitance and resistance extraction probl...
Single-level and multi-path interconnect structures embedded in dielectrics on a silicon substrate a...
This thesis describes the theory, simulation and experimental implementation of a method by which an...
The experimental characterization of gate capacitance in nanoscale devices is challenging. We report...
This paper proposes a novel charge-based Complementary Metal Oxide Semiconductor (CMOS) capacitive s...