Geometry scaling increases the relative effect of coupling capacitances on performance, power, and noise so that they need to be carefully taken into account during process development, characterization, and monitoring. In the last decade, charge-based capacitance measurements (CBCMs) have been widely used to estimate on-chip wiring and coupling capacitances because of their accuracy and simplicity. We provide a thorough theoretical and experimental study of CBCMs applied to the selective extraction of cross-coupling capacitances. We take a historical perspective starting from the original CBCM approach proposed by Chen in 1996, and we present a new technique for crosstalk-based capacitance measurements (CTCMs). CTCMs improve the accuracy a...
Abstract—In this paper, the on-wafer measurement of junction depletion capacitance is examined. This...
[[abstract]]Starting from CIEF (charge injection induced errors) CBCM (charge-based capacitance meas...
The experimental characterization of gate capacitance in nanoscale devices is challenging. We report...
Geometry scaling increases the relative effect of coupling capacitances on performance, power, and n...
Charge-based capacitance measurements (CBCMs) are widely used to estimate on-chip wiring capacitance...
We present a simple test structure (derived from the CBCM technique proposed by Sylvester et al.) th...
Interconnection parasitic capacitance is the dominant delay and noise source in modern integrated ci...
Interconnection parasitic capacitance is the dominant delay and noise source in modem integrated cir...
[[abstract]]In this letter, charge-based capacitance measurement (CBCM) is applied to characterize b...
[[abstract]]In this work, we describe a novel operation of charge-injection-induced error-free charg...
The measurement of capacitance by Charge Based Capacitor Measurement (CBCM) is the most widely used ...
The paper deals with a modified CBCM (Charge-Based Capacitance Measurements) method for nonlinear ca...
A method and a relative test structure for measuring the coupling capacitance between two interconne...
Crosstalk within cable bundles can degrade system performance. In systems that use shielded twisted-...
technical reportA novel approach to solving the accurate capacitance and resistance extraction probl...
Abstract—In this paper, the on-wafer measurement of junction depletion capacitance is examined. This...
[[abstract]]Starting from CIEF (charge injection induced errors) CBCM (charge-based capacitance meas...
The experimental characterization of gate capacitance in nanoscale devices is challenging. We report...
Geometry scaling increases the relative effect of coupling capacitances on performance, power, and n...
Charge-based capacitance measurements (CBCMs) are widely used to estimate on-chip wiring capacitance...
We present a simple test structure (derived from the CBCM technique proposed by Sylvester et al.) th...
Interconnection parasitic capacitance is the dominant delay and noise source in modern integrated ci...
Interconnection parasitic capacitance is the dominant delay and noise source in modem integrated cir...
[[abstract]]In this letter, charge-based capacitance measurement (CBCM) is applied to characterize b...
[[abstract]]In this work, we describe a novel operation of charge-injection-induced error-free charg...
The measurement of capacitance by Charge Based Capacitor Measurement (CBCM) is the most widely used ...
The paper deals with a modified CBCM (Charge-Based Capacitance Measurements) method for nonlinear ca...
A method and a relative test structure for measuring the coupling capacitance between two interconne...
Crosstalk within cable bundles can degrade system performance. In systems that use shielded twisted-...
technical reportA novel approach to solving the accurate capacitance and resistance extraction probl...
Abstract—In this paper, the on-wafer measurement of junction depletion capacitance is examined. This...
[[abstract]]Starting from CIEF (charge injection induced errors) CBCM (charge-based capacitance meas...
The experimental characterization of gate capacitance in nanoscale devices is challenging. We report...