VLSI implementation of 4×4 Mesh topology for network-on-chip

Nowadays, every electronic system, ranging from a small mobile phone to a satellite sent into space, has a System-on-Chip (SoC). Over the years, SoCs have undergone rapid evolution and are still progressing at a swift pace. But, due to this explosive evolution of semiconductor industry, the devices are scaling down at a rapid rate and hence, the SoCs today have become communication-centric. However, the existing bus architectures comprising of wires for global interconnection in SoC Designs are undergoing a design crisis as they are not able to keep up with the rate of scaling down of devices. In response to this crisis,Network-on-Chip (NoC) is an upcoming archetype, and is becoming a leading contender to replace the conventional bus architectures. Many Network-on-Chip topologies have been introduced in an attempt to tackle various chip architecture needs and routing techniques. A network simulator NS2 has been utilized in an attempt to simulate the functioning of some of the topologies like Mesh, Binary Tree, Torus and Butterfly Fat Tree (BFT). Their performances in various traffic scenarios has been assessed and compared taking throughput, maximum end-to-end latency and dropping probability as parameters. It can be inferred from simulation results that with respect to throughput and dropping probability, Torus topology has an upper hand over the others whereas BFT topology provides lower latency as compared to others. The Mesh topology is well-suited for incorporating regular-sized processing elements on a single chip. It is also quite simpler to design and incorporate various routing protocols into it as opposed to others. Thus, to validate the functioning of NoC on hardware, 4×4 Mesh architecture has been designed in VHDL and the same has been synthesized for Virtex II Pro FPGA