FPGA implementation of UTMI and protocol layer of USB 2.0

With the advancement in hardware technology, FPGA coming into existence are able to accommodate faster and more powerful electronic devices on a single device. IP Cores have been developed to enable design reuse, increasing functionality, performance and flexibility. USB is a serial bus which can realize the Plug and Play feature for easy connection of peripherals to PCs. It is a point to point interface in which data rate of over 480Mbit/s can be transferred as per new USB 2.0 Specification. It provides bi-directional, low- cost and high speed serial interface for data transfer. Multiple devices can be attached through a hub to the host. The USB Communication implemented complies with USB 2.0 Specifications essential for basic data transfer and can operate at USB Full speed (12 Mbit/s) and High speed (480Mbit/s). This project deals with implementation of a USB Core specifically UTMI and protocol layer module on FPGA. The design is done by writing code in verilog HDL which is then verified and synthesized using Xilinx XST. The result is verified using testbench waveform to study the transactions carried out by USB and how packet serialization and de-serialization, CRC addition,error checking is done