Architecture for SuperSpeed data communication for USB 3.0 device using FPGA

The need for very large speed data communication leads to use of USB 3.0. This can be achieved by mixing the advantage of parallel and serial data transfer. This project work provides architecture for communication between USB 3.0 device controller (Cypress CYUSB3014) and USB 3.0 host controller (TUSB7320) at a data rate of 5.0 Gbps using Altera’s Stratix IV (EP4SGX70DF29C3N) FPGA. To maintain synchronization between GPIF II and PCIe hard IP, two FIFO's are used. PLL is used to provide clock signal at various frequencies. The physical layer provides signalling technology for SuperSpeed bus. The functionality of physical layer for USB 3.0 has been implemented in this project. Physical layer is functionally segregated in two parts, namely, transmitter and receiver.In transmitter module, the implementation of scrambler, 8b/10b encoder and parallel to serial converter is simulated using ModelSim-Altera 6.6d. And in receiver section, the implementation of serial to parallel converter, 8b/10b decoder and descrambling is similarly implemented. Both these modules are realized in Altera’s Cyclone II (EP2C20F484C7) FPGA