Evaluation of Real-Time Linux on RISC-V processor architecture

Currently, many real-time systems are implemented either by carefully crafted bare-metal software or by utilizing some typical Real-Time Operating System. These are appropriate for relatively simple systems, but once other functional requirements increase, using a more feature-rich General Purpose Operating System such as Linux often becomes desirable. However, these types of operating systems are not designed to fulfill any real-time requirements, so special attention has to be paid when using them in real-time applications. For Linux, there are already multiple different projects that implement the desired real-time capabilities. One of them is the Real-Time Linux project, i.e., PREEMPT_RT patch, backed by the Linux Foundation. The purpose of this thesis was to study the Real-Time Linux operating system on RISC-V processor architecture. This combination was especially interesting, as it would allow a completely open Real-Time Linux computing stack, which has never been possible before. The development, testing, and measurements were mainly conducted on a recent RISC-V development board, but also an emulator platform was used. The latency measurements and analysis were done using a collection of standard tools, namely stress-ng, cyclictest and ftrace. The work initially began by porting the PREEMPT_RT patch to RISC-V architecture. During this stage, a couple of changes to the kernel were implemented to get the system properly functioning. Once the porting was finished, various latency measurements were executed to analyze the real-time characteristics under several system load conditions. In total, six stress categories were defined to thoroughly cover different parts of the system. These measurements were also repeated on a mainline Linux kernel to get a sufficient baseline. The results proved that the PREEMPT_RT patch considerably reduced the experienced latencies. Excluding the latencies measured in an out-of-memory error condition, the maximum latencies were consistently under 150 µs. Most importantly, the latencies were not significantly affected by the different kinds of system loads, making this setup, in theory, viable for many real-time systems. The results were also very comparable to prior research studies conducted with other processor architectures. Overall, this combination seems to be a very appealing option for implementing feature-rich real-time systems based entirely on open components. However, as the RISC-V architecture is not officially supported by the PREEMPT_RT patch, it cannot be yet recommended for practical applications