In this work, the fabrication of charge trapping memory cells with laser-synthesized indium-nitride nanoparticles (InN-NPs) embedded in ZnO charge trapping layer is demonstrated. Atomic layer deposited Al2O3 layers are used as tunnel and blocking oxides. The gate contacts are sputtered using a shadow mask which eliminates the need for any lithography steps. High frequency C-V-gate measurements show that a memory effect is observed, due to the charging of the InN-NPs. With a low operating voltage of 4V, the memory shows a noticeable threshold voltage (V-iota) shift of 2V, which indicates that InN-NPs act as charge trapping centers. Without InN-NPs, the observed memory hysteresis is negligible. At higher programming voltages of 10 V, a memory...
The memory effects of a three-layer nonvolatile memory device Al/C-60/ZnO nanoparticles embedded in ...
Ultrathin InP passivated GaAs non-volatile memory devices were fabricated with chemically synthesize...
In2O3 nanocrystal memories with barrier-engineered tunnel layers were fabricated on a p-type Si subs...
Cataloged from PDF version of article.In this work, the fabrication of charge trapping memory cells ...
A thin film ZnO charge trapping memory cell with embedded nanoparticles is demonstrated by Physics B...
In this work, a bottom-gate charge trapping memory device with Zinc-Oxide (ZnO) channel and 2-nm Si ...
A charge trapping memory with 2 nm silicon nanoparticles (Si NPs) is demonstrated. A zinc oxide (ZnO...
Cataloged from PDF version of article.A charge trapping memory with 2 nm silicon nanoparticles (Si N...
A charge trapping memory with graphene nanoplatelets embedded in atomic layer deposited ZnO (GNIZ) i...
In this work, the effect of embedding Silicon Nanoparticles (Si-NPs) in ZnO based charge trapping me...
In this study, non-volatile memory effect was characterized using the single-transistor-based memory...
Cataloged from PDF version of article.A charge trapping memory with graphene nanoplatelets embedded ...
Low-dimensional semiconductor nanostructures are of great interest in high performance electronic an...
[[abstract]]Silicon-oxide-nitride-oxide-silicon devices with nanoparticles (NPs) as charge trapping ...
The memory effects of a three-layer nonvolatile memory device Al/C-60/ZnO nanoparticles embedded in ...
The memory effects of a three-layer nonvolatile memory device Al/C-60/ZnO nanoparticles embedded in ...
Ultrathin InP passivated GaAs non-volatile memory devices were fabricated with chemically synthesize...
In2O3 nanocrystal memories with barrier-engineered tunnel layers were fabricated on a p-type Si subs...
Cataloged from PDF version of article.In this work, the fabrication of charge trapping memory cells ...
A thin film ZnO charge trapping memory cell with embedded nanoparticles is demonstrated by Physics B...
In this work, a bottom-gate charge trapping memory device with Zinc-Oxide (ZnO) channel and 2-nm Si ...
A charge trapping memory with 2 nm silicon nanoparticles (Si NPs) is demonstrated. A zinc oxide (ZnO...
Cataloged from PDF version of article.A charge trapping memory with 2 nm silicon nanoparticles (Si N...
A charge trapping memory with graphene nanoplatelets embedded in atomic layer deposited ZnO (GNIZ) i...
In this work, the effect of embedding Silicon Nanoparticles (Si-NPs) in ZnO based charge trapping me...
In this study, non-volatile memory effect was characterized using the single-transistor-based memory...
Cataloged from PDF version of article.A charge trapping memory with graphene nanoplatelets embedded ...
Low-dimensional semiconductor nanostructures are of great interest in high performance electronic an...
[[abstract]]Silicon-oxide-nitride-oxide-silicon devices with nanoparticles (NPs) as charge trapping ...
The memory effects of a three-layer nonvolatile memory device Al/C-60/ZnO nanoparticles embedded in ...
The memory effects of a three-layer nonvolatile memory device Al/C-60/ZnO nanoparticles embedded in ...
Ultrathin InP passivated GaAs non-volatile memory devices were fabricated with chemically synthesize...
In2O3 nanocrystal memories with barrier-engineered tunnel layers were fabricated on a p-type Si subs...