International audienceThis paper proposes a 4-node-upset (4NU) recoverable and high-impedance-state (HIS) insensitive latch design, namely QRHIL, for highly robust computing in harsh radiation environments. The latch mainly comprises a 5×5 looped C-element matrix to store values and provide complete 4NU recovery. Owing to the multiple-level error-interception of the 5×5 C-element matrix, the latch can recover from all possible 4NUs; thus, the latch is insensitive to HIS. Simulation results demonstrate the 4NU-recovery of the proposed latch. The results also show that the latch can approximately save 46% D-Q delay and 46% CLK-Q delay owing to the use of a high-speed D-Q path and clock-gating, compared with the state-of-the-art 3NU-recoverabl...
When exposed to an harsh environment in space, high atmosphere or even on earth, Integrated Circuits...
This work was supported in part by the Spanish MCIN/AEI /10.13039/501100011033/ FEDER under Grant PI...
A single event causing a double-node upset is likely to occur in nanometric complementary metal-oxid...
International audienceThis paper proposes a 4-node-upset (4NU) recoverable and high-impedance-state ...
To avoid soft errors in integrated circuits, this paper presents two high-performance latch designs,...
International audienceAs the CMOS technology is continuously scaling down, nano-scale integrated cir...
International audienceIn deep nano-scale and high-integration CMOS technologies, storage circuits ha...
International audienceWith the aggressive reduction of CMOS transistor feature sizes, the soft error...
Due to semiconductor technology scaling, integrated circuits have become more sensitive to soft erro...
A high-performance and low power consumption triple-node upset self-recoverable latch (HTNURL) is pr...
International audienceTo meet the requirements of both costeffectiveness and high reliability for lo...
The charge sharing effect is becoming increasingly severe due to the continuous reduction of semicon...
International audienceWith the advancement of semiconductor technologies, nano-scale CMOS circuits h...
International audienceFirst, this paper proposes a double-node-upset (DNU)-completely-tolerant (DNUC...
International audienceIn space, the impact of radiative particles, such as neutrons and heavy ions, ...
When exposed to an harsh environment in space, high atmosphere or even on earth, Integrated Circuits...
This work was supported in part by the Spanish MCIN/AEI /10.13039/501100011033/ FEDER under Grant PI...
A single event causing a double-node upset is likely to occur in nanometric complementary metal-oxid...
International audienceThis paper proposes a 4-node-upset (4NU) recoverable and high-impedance-state ...
To avoid soft errors in integrated circuits, this paper presents two high-performance latch designs,...
International audienceAs the CMOS technology is continuously scaling down, nano-scale integrated cir...
International audienceIn deep nano-scale and high-integration CMOS technologies, storage circuits ha...
International audienceWith the aggressive reduction of CMOS transistor feature sizes, the soft error...
Due to semiconductor technology scaling, integrated circuits have become more sensitive to soft erro...
A high-performance and low power consumption triple-node upset self-recoverable latch (HTNURL) is pr...
International audienceTo meet the requirements of both costeffectiveness and high reliability for lo...
The charge sharing effect is becoming increasingly severe due to the continuous reduction of semicon...
International audienceWith the advancement of semiconductor technologies, nano-scale CMOS circuits h...
International audienceFirst, this paper proposes a double-node-upset (DNU)-completely-tolerant (DNUC...
International audienceIn space, the impact of radiative particles, such as neutrons and heavy ions, ...
When exposed to an harsh environment in space, high atmosphere or even on earth, Integrated Circuits...
This work was supported in part by the Spanish MCIN/AEI /10.13039/501100011033/ FEDER under Grant PI...
A single event causing a double-node upset is likely to occur in nanometric complementary metal-oxid...