A Massively Parallel RNS Architecture

In this paper parallelism on the algorithmic, architectural, and arithmetic levels is exploited in the design of a Residue Number System (RNS) based architecture. The architecture is based on modulo processors. Each modulo processor is implemented by two dimensional systolic array composed of very simple cells. The decoding stage is implemented using a 2-D array, too. The decoding bottleneck is eliminated. The whole architecture is pipelined which leads to high throughput rate.http://ieeexplore.ieee.org.libproxy.bridgeport.edu/stamp/stamp.jsp?tp=&arnumber=18648