Pico Processor Using Verilog HDL

© ASEE 2009The Pico processor is a scaled down RISC processor hence the name “Pico”. Pico processors form an integral part in a network. They act as co-processors to Network processors. The network processors are in-charge of various complex functions such as routing, packet switching, queuing, encryption, decryption, pattern matching, computation and other such tasks. Many Pico processors work in parallel with the network processor, which leads to reduced computing time and improved performance (speed). This in turn increases the processing power of the network processor. One of the main uses of the Pico processor is to take care of the computation part of the network processor. Our project aims to further improve the performance of the network processor by increasing the processing speed of the Pico processor. We can do this by altering the architecture of the current Pico processors to accommodate a five stage pipeline. By doing so, we can manage to increase the speed of execution of each instruction by up to five times. The five stages which we have incorporated in our architecture are Instruction Fetch, Instruction Decode, Execute, Memory I/O and Write Back. The Pico processor is designed and simulated with ModelSim 6.2c. The logic synthesis of the Pico processor is performed using Quartus II software. The simulation results demonstrate the correct functions of the designed Pico processor. Significant performance enhancement has been observed in the designed Pico processor